Mixed Signal Digital Design Engineer (m/f)

      NXP Semiconductors Austria GmbH Standort Gratkorn

      Gratkorn - vor 3 Monaten

      Mixed Signal Digital Design Engineer (m/f)



      NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets.

      Your responsibilities:

      • Developing a mixed signal low power system-on-chip for the automotive product solutions
      • Definition and execution of all mixed signal digital design aspects from concept definition, RTL design, DfT insertion, MS verification, timing & power constraint definition, synthesis and assistance in mixed signal P&R.
      • Assist the system engineer with all aspects of system engineering specifically building the low level configuration APIs or hardware abstraction layers (HAL)
      • Close collaboration with SoC architects, analogue & digital design engineers, verification engineers, and embedded software engineers.

      Your profile:

      • BS/MS in EE and 5+ years of hands-on experience in automotive Mixed Signal SoC/IP development
      • Extensive knowledge and experience in front-end implementation tasks such as CONSTRAIN (timing & power) definition, synthesis, power aware LEC, and STA.
      • Deep knowledge in power aware verification including static and dynamic verification
      • Experience in developing and supporting automation across the SoC development flow
      • Excellent scripting skills (TCL, Perl, Shell scripts)
      • Previous experience in low power, high performance, high throughput designs especially in communication protocols
      • Strong knowledge in on-chip bus protocols: AMBA, AXI, AHB, Wishbone, OCP, or similar
      • Capable of turning requirements into executable models in MATLAB/SIMULINK or similar
      • Industry exposure to and knowledge in subsystem/chip-let or chip P&R
      • Exposure to Cadence MSoT flow or similar
      • Excellent verbal and written communication skills
      • Proficient in industry standard EDA tools

      NXP offers competitive compensation. Due to Austrian law we are obliged to state the minimum gross salary according to legal regulations and for this role this amounts to EUR 46.000 gross. Depending on experience and education higher remuneration is possible.
      Moreover, we provide attractive benefits to our employees.

      NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.




      About Us

      Our people are the heart and soul of our business. Their talent enables NXP to continue providing Secure Connections for a Smarter World. Helping every employee to be the best that they can be is a core part of our philosophy. This means creating the right environment for individuals to flourish, with ample opportunities for career development.