Senior SOC AMS Verification Engineer (m/f/d)

      NXP Semiconductors Austria GmbH Standort Gratkorn

      Gratkorn - vor 1 Monat

      Senior SOC AMS Verification Engineer (m/f/d)

      Gratkorn

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      NXP Semiconductors N.V. enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 30,000 employees in more than 30 countries and posted revenue of $9.41 billion in 2018.

      As part of the Analog Mixed-Signal Verification Team you will be in charge to develop the framework and the most efficeint strategies to verify the System functionality at Chip-Top Level through mixed-mode simulations covering Analog, Digital and Memories. You will review and execute the Verification Plan and you will deliver results in the agreed format to the project Verification Lead.

      Your Responsibilities:

      Define the AMS Verification Plan for each project

      Set-up an efficient AMS Verification flow and harmonize it with the Digital Verification flow

      Execute the Verification Plan by running the AMS regressions

      Employ techniques for minimizing simulation time and maximizing verification coverage

      Report, debug and drive the resolution of each fail found, interfacing with the different domains: Analog, Digital, Test, Architecture, Project Management

      Document the implemented workflow and the obtained results at the end of each project

      Keep yourself up-to-date with the latest verification methodologies by attending trainings and courses, reading state-of-the-art literature, etc.

      Your Profile:

      Master Degree in Electrical / Electronic Engineering or similar

      5 years of experience in ChipTop / System Level AMS Verification

      Ability to visually inspect analog circuits and/or digital modules to be able to:

      grasp their main functionalities;

      write / review a WREAL or VerilogAMS model out of an analog circuit;

      Knowledge of both the Analog and Digital Design flows, with hands-on experience on Analog Design

      Proven language knowledge: Verilog / VerilogAMS, SystemVerilog, WREAL

      Scripting knowledge: Linux Bash, Tcl

      Knowledge of the UVM flow and of formal verification

      Knowledge of the following languages and tools is an advantage:

      C/C++, Perl, Python, Tcl, (V)HDL

      Cadence Virtuoso / Spectre, Cadence Incisive suit

      Revision Control Tools (Design Sync, SVN)

      Engaged, willing-to-learn and enthusiastic team player, possessing good communication skills

      Ability to drive tasks involving different domain-experts (Architecture, Analog, Digital, PM)

      NXP offers competitive compensation. Due to Austrian law we are obliged to state the minimum gross salary according to legal regulations and for this role this amounts to EUR 56.000 gross. Depending on experience and education higher remuneration is possible. Moreover, we provide attractive benefits to our employees.

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      FULLTIME

      R-10019130

      About Us

      Our people are the heart and soul of our business. Their talent enables NXP to continue providing Secure Connections for a Smarter World. Helping every employee to be the best that they can be is a core part of our philosophy. This means creating the right environment for individuals to flourish, with ample opportunities for career development.